Semiconductor dynamic random access memories (DRAMs) are typically formed of wordlines and columns crossing the wordlines. Capacitors adjacent each crossing of the rowlines and columns store charge, designating the data to be stored. The capacitors are coupled to the columns by an access transistor in order to receive or discharge charge upon receipt of an appropriate voltage on the rowlines. The rowlines and columns are selected so as to read and write to particular capacitors by means of row (or X) decoders and columns (or Y) decoders.
There are sometimes physical faults associated with the columns or associated elements. For this reason, RAMs usually contain redundant (spare) columns which involve the provision of extra memory elements and column circuitry. The extra memory and required redundant decoders to access that memory in place of defective columns uses valuable semiconductor chip area and decreases the area efficiency of the memory.
Various techniques have been implemented to provide column redundancy schemes in synchronous dynamic random access memories (SDRAMs). Amongst these are the address compare approach, the address detector approach, the shifter approach, and the address or data steering approach as well as combinations thereof. For example, in a first of these techniques utilizes an Y address comparator, wherein predecoded Y address signals (PY1:N) pass through fuses to generate redundant column enable signals (RCE) as illustrated in FIG. 1. The fuses associated with the redundancy comparator 2 having inherent capacitance and resistance add an extra delay in the Y redundant path.
A second technique involves an Y address detector 4 wherein Y address signals (AY(N-1:0) control NMOS gates that connect to a pre-charged node through fuses and each can generate redundant column enable signals as shown in FIG. 2. When a Y address matches a fuse programming pattern, a column redundant enable signal (COL.sub.-- RED.sub.-- EN) is maintained high in order to indicate that the column corresponding to the current Y address will be replaced by a redundant one. Because of this redundancy detecting circuit, timing between the normal and the redundant column path is usually different. Additional logic circuits are required to adjust the timing difference, i.e. a time delay circuit must be employed in the normal address signal path in order to compensate for the slower redundant path.
A further technique known as a shift replacement Y decoder utilizes fuses in the Y decoders but not connected in the signal path. Generally, two Y select lines share one group of fuses. In order to replace a column, the column is disabled by blowing the fuse inside the Y decoder. Shifting the Y driver access for the defective block over to an adjacent driver completes replacement. An advantage of this system is that since fuses are not connected in the column address path, no difference in timing between the normal and redundant path exists. Furthermore, block replacement is possible (failed columns can be repaired in each block with different decoding of each block). A disadvantage of this system is that two adjacent Y select lines must be replaced at the same time making this technique less flexible than other techniques. Furthermore, one directional shifting is required of the columns.
In FIG. 3, a redundancy circuitry 10 is implemented which uses an address steering approach according to an embodiment of the invention in U.S. patent application Ser. No. 08/904,153 to Chen et al. assigned to MOSAID Technologies Inc. In this approach, each Y decoder consists of an NMOS multiplexer 12 which steers the column select signal either down the normal or redundant paths according to the information programmed in the fuse circuit 14. NMOS transistors are used in conjunction with an on-chip boosted voltage supply VPP to select the appropriate path since the NMOS transistors in the multiplexer require a voltage larger than VDD to fully turn them on. The redundant select line RYSEL 16 is long and exhibits considerable RC delay. In this implementation two redundant column drivers are accessible by 64 normal columns, but the redundant drivers are dedicated to replacing faulty columns only in that block and can not be used to replace faulty columns in any other blocks within a quadrant. This lack of flexibility proves to be intolerable when moving from the 64M SDRAM density to the 256M SDRAM density. Furthermore, the length of the RYSEL line 16 makes such a design too slow for the 256M generation SDRAM.
Thus, it may be seen that there is a need for a redundancy scheme that reduces the timing difference between normal and redundant column paths and which reduces the number of fuses and provides greater flexibility in repairing faulty columns and is capable of accommodating the speed requirements of large memories.